The present invention relates generally to the field of semiconductor devices, and more particularly to memory devices. Still more particularly, the invention relates to methods for programming semiconductor memory devices by stressing polycrystalline silicon resistors.
Polycrystalline silicon is used for various purposes in semiconductor devices. For example, it is commonly used as a conductive material such as gate electrodes in metal oxide semiconductor (MOS) transistors. It may be used as a diffusion source on a semiconductor body, or as a resistive material. The electric conductivity of polycrystalline silicon may be influenced by a variety of factors, including but not limiting to: the choice of dopant, dopant density, polycrystalline grain size, polycrystalline geometries, and stress time.
Dopants are elements introduced to semiconductor to establish conductivity. Common N-type dopants in silicon include phosphorous (P), arsenic (As) and antimony (Sb). As an example, carbon is also a known dopant in polycrystalline silicon. When there is a low level of carbon, electric resistance and activation energy of the polycrystalline silicon decrease when carbon concentration increases. The decrease in resistance and activation energy is due to the presence of carbon atoms at the boundaries of silicon crystallites, which increases the mobility of charge carriers over the grain limits. When carbon concentration in polycrystalline silicon is further increased, both the resistance and activation energy of the resistance increase. This is attributable to the presence of silicon carbide and/or carbon beside the polycrystalline silicon. When carbon concentration is further increased, both resistance and activation energy of resistance decrease. The comparative low levels of resistance and activation energy are attributable to conductivity via carbon bridges.
Typically, polycrystalline silicon resistors are formed in a dielectric layer overlying the silicon substrate. The initial conductivity of the polycrystalline silicon resistor is determined chiefly by both the concentration of and the homogeneity of distribution of the implanted dopants in the polycrystalline material. As an example, phosphorous (stable isotope: P-31) is used as dopant. The phosphorous-doped polycrystalline silicon can be prepared by implanting P-31 ions into an oxidized silicon substrate. Depending on the concentration of P-31 ions, and how they are distributed, the conductivity of the polycrystalline silicon resistor may vary significantly. For example, if there are not enough P-31 ions, conductivity will remain low across the polycrystalline silicon resistor. Even if there are enough P-31 ions, but if they are not distributed uniformly over the geometry of the polycrystalline silicon resistor, conductivity will still remain low.
Polycrystalline silicon is made up of grains or crystallites of silicon. The properties of these grains, including grain size, inter-grain distances and grain density, can materially affect the conductivity of the polycrystalline silicon resistor. The geometry of the polycrystalline silicon resistor also affects its conductivity. Generally, the geometry is chosen to avoid complications of edge effects inherent at minimum geometries and to provide stress characteristics dominated by the film properties alone.
When the polycrystalline silicon resistor is stressed, various factors can influence subsequent conductivity. First, defects in the grain boundary of the polycrystalline silicon resistor trap electrons, thereby reducing the average mobility of these electrons. As the stressing current increases, more electrons can have enough energy to escape the electron trap, thereby increasing conductivity. Second, stressing current generates heat energy, which raises temperature of the polycrystalline silicon resistor. The generated heat energy assists implanted ions to segregate from grain region into grain boundary, thereby filling the defects within the grain boundary and increasing conductivity. Finally, the increase in heat energy leads to lattice vibration and electron collision, both of which decrease conductivity.
As stressing current increases, conductivity increases due to electrons escaping grain traps and ions segregating from grain region into grain boundary. As stressing current further increases, conductivity decreases due to the increases in lattice vibration and electron collision. However, the increase in conductivity due to escaping electrons and segregating ions overweighs the decrease in conductivity due to lattice vibration and electron collision. As stressing current further increases, grain boundary melting occurs, thereby further increasing conductivity. Although ion segregation can be reversed, i.e. dopant atoms diffuse from the grain boundaries back to the grain region, it can only be achieved through Joule heating. Therefore, without Joule heating, it is difficult to reverse ion segregation. As such, conductivity of the polycrystalline silicon resistor will be permanently increased. In other words, the resistivity of the polycrystalline silicon resistor will be permanently decreased.
Through controlled ion segregation, it is therefore possible to precisely control the final resistor value. Compensation techniques, such as Joule heating or further current stressing can be used to fine-tune a resistor's resistivity. In other words, the polycrystalline silicon resistor can be programmed by stressing it with a stressing current. Used in a memory circuit, the permanent change to the resistivity of the polycrystalline silicon resistor in effect “stores” a specific memory state. A plurality of polycrystalline silicon resistors allow one to act as the programmed state while the other as the reference state. A comparison of the two resistor values therefore yields valuable memory information.
Desirable in the art of semiconductor memory design are additional methods and materials through which one-time programming of non-volatile data can be achieved.